1. Field of the Invention
The present invention relates to a semiconductor device having an SRAM (Static Random Access Memory) cell being capable of securing high reliability and a method for manufacturing the same.
2. Description of the Related Art
As a method of decreasing an occupied area of a chip by an SRAM, a method of constituting a load resistor (resistance element) by a high-resistance polycrystalline silicon film having a high resistance exists. Such a SRAM cell is called a high-resistance polycrystalline silicon load resistor type cell. The resistance element constituted by a high-resistance polycrystalline silicon film is stacked on the upper layer of MOS transistors constituting the SRAM cell. In this manner, an occupied area by the SRAM is reduced.
FIG. 1 is an equivalent circuit diagram showing the arrangement of an SRAM cell. In the SRAM cell, a flip-flop connected between a power supply Vcc and a ground potential Vss is arranged. The flip-flop is constituted by driver transistors Tr1 and Tr2, load resistors R1 and R2, and a cross wirings. A connection point of one terminal of the load resistor R1, one terminal of the driver transistor Tr1, and the gate of the driver transistor Tr2 serves as a storage node Q1. Similarly, a connection point of one terminal of the load resistor R2, one terminal of the driver transistor Tr2, and the gate of the driver transistor Tr1 serves as a storage node Q2. When data are held in the SRAM cell, data "High" and data "Low" are stored in each of the storage nodes.
One terminal of an access transistor Tr3 is connected to the storage node Q1, and one terminal of an access transistor Tr4 is connected to the storage node Q2. A word line WL is connected to the gates of the access transistors Tr3 and Tr4. A bit line BL1 is connected to the other terminal of the access transistor Tr3, and a bit line BL2 is connected to the other terminal of the access transistor Tr4.
The resistance value of a supply portion of the power supply Vcc, the resistance value of the cross wiring between the storage node Q1 and the driver transistor Tr2, and the resistance value of the cross wiring between the storage node Q2 and the driver transistor Tr1 are preferably set to be approximately several K.OMEGA./sq. or less to secure high reliability for the following reason. When the resistance value of the cross wirings exceeds the value described above, data transfer is delayed during data inversion of the memory cell, and a high-speed stable operation of the memory cell is hindered.
On the other hand, the load resistors R1 and R2 require resistances of about several G.OMEGA. to several T.OMEGA. or more because the SRAM cell is demanded to have a low power consumption. For example, when data "High" is stored in the storage node Q1, the driver transistor Tr2 is set in an ON state, and a through current flows from the power supply Vcc to the ground potential Vss through the load resistor R2 and the driver transistor Tr2. At this time, when the resistance value of the load resistor R2 is lower than the required resistance value, an excessive current flows from the power supply Vcc to the ground potential Vss as a standby current. Therefore, a power consumption of the SRAM increases. A similar operation is also performed when the data "High" is stored in the storage node Q2. For this reason, the load resistors R1 and R2 require extremely high resistances.
The high-resistance polycrystalline silicon load resistor type cell is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-219494. FIG. 2 is a sectional view showing a conventional semiconductor device described in Japanese Patent Application Laid-Open No. 9-219494.
A field oxide film 202 functioning as an element isolation region is formed at the surface of a semiconductor substrate 201. A gate oxide film 203 is formed on the semiconductor substrate 201. The field oxide film 202 and the gate oxide film 203 are shown as the same layer for descriptive convenience. A channel region is formed at the surface of the semiconductor substrate 201 below the gate oxide film 203. Source-drain regions (not shown) are formed on both the side portions of the channel region. A gate electrode 204 is formed on the gate oxide film 203. A driver MOS transistor having the gate electrode 204, the gate oxide film 203, the channel region, and the source-drain regions is formed.
In addition, in a region, at the surface of the semiconductor substrate 201, in which the gate electrode 204 is not formed, an N.sup.+ -diffusion layer 207, which is one of source-drain regions of an access MOS transistor, is selectively formed. An interlayer insulating film 208 in which a common contact hole 209 is provided is formed on the entire surface of the resultant structure. The common contact hole 209 is formed in a region corresponding to any one of the storage nodes of the SRAM cell. A pad polycrystalline silicon layer 210 is formed in the common contact hole 209 and selectively on the interlayer insulating film 208. The pad polycrystalline silicon layer 210 is constituted by a low-resistance polycrystalline silicon film. The pad polycrystalline silicon layer 210 is formed in a region corresponding to the storage node and the cross wiring between the storage node and the driver transistor connected thereto. A resistance polycrystalline silicon layer 212 is selectively formed on the pad polycrystalline silicon layer 210 and the interlayer insulating film 208. The resistance polycrystalline silicon layer 212 is constituted by a high-resistance polycrystalline silicon film. The resistance polycrystalline silicon layer 212 is formed in a region corresponding to a resistance element formed on the MOS transistor, i.e., a load resistor.
Of the resistance polycrystalline silicon layer 212, a portion directly formed on the interlayer insulating film 208 on the MOS transistor functions as the high-resistance load resistor. The length of the portion is called a resistor length. As the resistor length increases, the resistance of the load resistor in the SRAM cell increases.
The SRAM cell is manufactured in the following manner. FIGS. 3A to 3F are sectional views sequentially showing the steps in a method of manufacturing the conventional semiconductor device.
As shown in FIG. 3A, the field oxide film (silicon oxide film) 202 serving as an element separation region is formed at the surface of the semiconductor substrate 201. A silicon oxide film and a tungsten polycide film are sequentially stacked. These films are patterned to form the gate oxide film 203 and the gate electrode 204. The N.sup.+ -diffusion layer 207 serving as an impurity diffusion layer of an access transistor is selectively formed at the surface of the semiconductor substrate 201. At this time, source-drain regions (not shown) of a driver transistor are formed.
Thereafter, as shown in FIG. 3B, the interlayer insulating film 208 is formed on the entire surface of the resultant structure, and a mask for opening a contact hole is formed on the interlayer insulating film 208 by a resist 241. The common contact hole 209 is formed in the interlayer insulating film 208, and the resist 241 is removed.
Thereafter, as shown in FIG. 3C, the pad polycrystalline silicon layer 210 constituted by a low-resistance polycrystalline silicon film is formed on the entire surface of the resultant structure. In addition, a resist 242 having a predetermined shape is formed on the pad polycrystalline silicon layer 210. In general, an impurity is implanted in the pad polycrystalline silicon layer 210 at a high concentration to reduce the resistance thereof.
Thereafter, the pad polycrystalline silicon layer 210 is etched by using the resist 242 as a patterning mask. Then, as shown in FIG. 3D, the resist 242 is removed.
Thereafter, as shown in FIG. 3E, the resistance polycrystalline silicon layer 212 constituted by a high-resistance polycrystalline silicon film is formed, and a resist 243 having a predetermined shape is formed on the resistance polycrystalline silicon layer 212.
Thereafter, the end portion of the resistance polycrystalline silicon layer 212 is etched by using the resist 243 as a mask. With the steps, as shown in FIG. 3F, an SRAM cell having the structure shown in FIG. 2 can be obtained.
However, since an impurity is implanted in the pad polycrystalline silicon layer 210 at a high concentration to reduce the resistance, the impurity implanted in the pad polycrystalline silicon layer 210 tends to be diffused in a portion of the resistance polycrystalline silicon layer 212 being in contact with the pad polycrystalline silicon layer 210. FIG. 4 is a sectional view showing diffusion of an impurity in a conventional semiconductor device. As indicated by arrows in FIG. 4, the impurity is diffused from the end portion of the pad polycrystalline silicon layer 210 into the resistance polycrystalline silicon layer.
For securing a high resistance value, an amount of impurity implanted in the resistance polycrystalline silicon layer 212 is considerably lower than an amount of impurity implanted in the pad polycrystalline silicon layer 210. Therefore, a high-resistance portion in the resistance polycrystalline silicon layer 212 is shortened by the impurity diffused from the upper and side surfaces of the pad polycrystalline silicon layer 210. As a result, as shown in FIG. 4, although a resistor length L1 is originally supported, a resistor length L2 is actually obtained. More specifically, the resistor length is smaller than the predicted length.
Therefore, in the SRAM cell of the prior art described above, since the resistance of the load resistor is lower than the desired one, a problem is posed from the viewpoint of a reduction in power consumption.
There is a semiconductor device in which a common contact hole having a different shape is formed. FIG. 5 is a sectional view showing a conventional semiconductor device in which the opening portion of a common contact hole is located immediately above a diffusion layer. In this conventional semiconductor device, as in the semiconductor device described above, a semiconductor substrate 301, a field oxide film 302, a gate oxide film 303, a gate electrode 304, an N.sup.+ -display layer 307, an interlayer insulating film 308, a pad polycrystalline silicon layer 310, and a resistance polycrystalline silicon layer 312 are provided. In a common contact hole 309 provided in the interlayer insulating film 308, the lower end of the opening portion is located immediately above the N.sup.+ -display layer 307.
Even in the conventional semiconductor device arranged as described above, similarly, an impurity is diffused from the upper and side surfaces of the pad polycrystalline silicon layer 310 into the resistance polycrystalline silicon layer 312. Therefore, due to diffusion of the impurity, the high-resistance portion in the resistance polycrystalline silicon layer 312 is disadvantageously shorter than the high-resistance portion which is originally supposed.
The second conventional semiconductor device also has a problem on manufacturing. For example, when an alignment error to the common contact hole 309 occurs in the resist used for patterning the resistance polycrystalline silicon layer 312, the semiconductor substrate 301 may be etched.
FIG. 6 is a sectional view showing an inconvenience 25 caused by an alignment error. For example, assuming that a resist 313 is formed near an error position shown in FIG. 6, when etching is performed by using the resist 313 as a mask, the resistance polycrystalline silicon layer 312 and the pad polycrystalline silicon layer 310 are etched in the common contact hole 309 along one side surface of the resist 313. It is generally known that, when etching is performed, over-etching is performed in consideration of variations in process.
For this reason, when the alignment error of the resist 313 occurs, as shown in FIG. 6, the semiconductor substrate 301 is etched by over-etching. When the semiconductor substrate 301 immediately below the common contact hole 309 is etched, since a portion near the etched portion corresponds to a storage node of the SRAM cell, leakage is caused by damage of the substrate and such, and a serious problem that the stored data is broken is posed. Therefore, in such a case, the yield decreases.